- clock
: ipcore
- cmd
: flit_data, payload_hdr
- cntrlID
: OutputChannel< num_ip >, InputChannel< num_op >
- cols
: NoC
- cr_sig_fromE
: signals
- cr_sig_fromS
: signals
- cr_sig_toE
: signals
- cr_sig_toS
: signals
- credit_in
: OutputChannel< num_ip >, NWTile< num_nb, num_ic, num_oc >, ipcore
- credit_out
: NWTile< num_nb, num_ic, num_oc >, InputChannel< num_op >
- creditIC_CS
: NWTile< num_nb, num_ic, num_oc >
- ctime
: sim_hdr
- ctr
: NWTile< num_nb, num_ic, num_oc >
- cycles_per_flit
: TrafficGenerator
- payload
: flit_hdr
- pkt_interval
: CBRTraffic, BurstyTraffic
- pkt_size
: CBRTraffic, BurstyTraffic
- pkthdr
: flit
- pktid
: noc_hdr
- pkttype
: flit
- pntr
: fifo
- portE
: VCAllocator< num_ip >, OutputChannel< num_ip >, InputChannel< num_op >, Controller< num_ip >, BaseNWTile
- portN
: VCAllocator< num_ip >, OutputChannel< num_ip >, InputChannel< num_op >, Controller< num_ip >, BaseNWTile
- portS
: VCAllocator< num_ip >, OutputChannel< num_ip >, InputChannel< num_op >, Controller< num_ip >, BaseNWTile
- portW
: VCAllocator< num_ip >, OutputChannel< num_ip >, InputChannel< num_op >, Controller< num_ip >, BaseNWTile
- r_in
: OutputChannel< num_ip >
- r_vc
: OutputChannel< num_ip >
- ran_var
: ipcore
- rdy
: NWTile< num_nb, num_ic, num_oc >
- regs
: fifo
- rem
: BurstyTraffic
- rnum
: CBRTraffic
- route
: AntNet_hdr, source_hdr
- route_info
: TrafficGenerator
- rows
: NoC
- rtable
: Controller< num_ip >
- rtalgo
: ant_hdr, flit_head
- rthdr
: ant_hdr, flit_head
- rtReady
: NWTile< num_nb, num_ic, num_oc >, InputChannel< num_op >, Controller< num_ip >
- rtReq
: NWTile< num_nb, num_ic, num_oc >
- rtRequest
: InputChannel< num_op >, Controller< num_ip >
- sig_fromE
: signals
- sig_fromS
: signals
- sig_toE
: signals
- sig_toS
: signals
- sigs
: NoC
- sim_count
: ipcore, InputChannel< num_op >
- simdata
: flit
- sourceAddress
: InputChannel< num_op >, Controller< num_ip >
- sourcehdr
: routing_hdr
- src
: flit
- srcAddr
: NWTile< num_nb, num_ic, num_oc >
- switch_cntrl
: VCAllocator< num_ip >, OutputChannel< num_ip >, NWTile< num_nb, num_ic, num_oc >, NoC, InputChannel< num_op >, Controller< num_ip >
Generated on Mon May 7 19:03:19 2007 for NIRGAM by
1.3.9.1