#include <OutputChannel.h>
Inheritance diagram for OutputChannel< num_ip >:
Public Member Functions | |
SC_CTOR (OutputChannel) | |
Constructor. | |
void | entry () |
reads and processes incoming flit | |
void | closeLogs () |
void | setTileID (UI tileID, UI portN, UI portS, UI portE, UI portW) |
sets tile ID and id corresponding to port directions | |
Public Attributes | |
sc_in< flit > | inport [num_ip] |
input data/flit ports (one for each IC) | |
sc_out< bool > | inReady [num_ip] |
output port to send ready signal to IC | |
sc_in< bool > | switch_cntrl |
clock input port | |
sc_out< flit > | outport |
output data/flit port | |
sc_in< creditLine > | credit_in [NUM_VCS] |
input port to recieve credit info (buffer status) from ICs of neighbor tiles | |
UI | tileID |
unique tile ID | |
UI | cntrlID |
control ID to identify channel direction (N, S, E, W, C) | |
UI | portN |
port number representing North direction | |
UI | portS |
port number representing South direction | |
UI | portE |
port number representing East direction | |
UI | portW |
port number representing West direction | |
switch_reg | r_in [num_ip] |
registers to store flit from inport, one for each inport | |
switch_reg | r_vc [NUM_VCS] |
registers, one for each next VCID | |
ULL | latency |
total latency | |
ULL | num_pkts |
total number of packets | |
ULL | num_flits |
total number of flits | |
ULL | input_time |
generation timestamp of head flit of a packet | |
float | avg_latency |
average latency (in clock cycles) per packet | |
float | avg_latency_flit |
average latency (in clock cycles) per flit | |
float | avg_throughput |
average throughput (in Gbps) | |
int | beg_cycle |
clock cycle in which first flit is recieved in the channel | |
int | end_cycle |
clock cycle in which last flit leaves the channel | |
int | total_cycles |
total number of clock cycles |
This module defines an Output Channel in a network tile
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closes logfiles at the end of simulation and computes performance stats |
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reads and processes incoming flit Process sensitive to inport event and clock event
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Constructor.
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sets tile ID and id corresponding to port directions Method to assign tile IDs and port IDs |
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average latency (in clock cycles) per packet
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average latency (in clock cycles) per flit
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average throughput (in Gbps)
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clock cycle in which first flit is recieved in the channel
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control ID to identify channel direction (N, S, E, W, C)
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input port to recieve credit info (buffer status) from ICs of neighbor tiles
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clock cycle in which last flit leaves the channel
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input data/flit ports (one for each IC)
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generation timestamp of head flit of a packet
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output port to send ready signal to IC
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total latency
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total number of flits
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total number of packets
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output data/flit port
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port number representing East direction
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port number representing North direction
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port number representing South direction
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port number representing West direction
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registers to store flit from inport, one for each inport
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registers, one for each next VCID
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clock input port
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unique tile ID
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total number of clock cycles
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