#include <VCAllocator.h>
Inheritance diagram for VCAllocator< num_ip >:
Public Member Functions | |
SC_CTOR (VCAllocator) | |
Constructor. | |
void | allocate_VC () |
process sensitive to VC request | |
void | update_credit () |
void | setTileID (UI tileID, UI portN, UI portS, UI portE, UI portW) |
sets tile ID and id corresponding to port directions | |
sc_uint< VCS_BITSIZE+1 > | getNextVCID (int, int) |
allocates vcid in the requested channel | |
Public Attributes | |
sc_in< bool > | switch_cntrl |
input clock port | |
sc_in< bool > | vcRequest [num_ip] |
input ports for request signals from ICs | |
sc_in< sc_uint< 2 > > | opRequest [num_ip] |
input ports to recieve output channel requested from ICs | |
sc_out< sc_uint< VCS_BITSIZE+1 > > | nextVCID [num_ip] |
output ports to send next VCID to ICs | |
sc_out< bool > | vcReady [num_ip] |
output ports to send ready signal to ICs | |
sc_in< creditLine > | Icredit [num_ip][NUM_VCS] |
input ports to recieve credit info (buffer status) from ICs | |
bool | vcFree [num_ip][NUM_VCS] |
status registers to store credit info (buffer status) | |
UI | tileID |
TileID. | |
UI | portN |
port number representing North direction | |
UI | portS |
port number representing South direction | |
UI | portE |
port number representing East direction | |
UI | portW |
port number representing West direction |
This module defines a Virtual channel allocator (VCA) in a network tile
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process sensitive to VC request Process sensitive to incoming request for virtual channel allocation
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allocates vcid in the requested channel Method that implements virtual channel allocation Parameters:
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Constructor.
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sets tile ID and id corresponding to port directions Method to assign tile IDs and port IDs |
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process sensitive to credit input, updates credit (buffer status) |
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input ports to recieve credit info (buffer status) from ICs
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output ports to send next VCID to ICs
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input ports to recieve output channel requested from ICs
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port number representing East direction
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port number representing North direction
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port number representing South direction
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port number representing West direction
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input clock port
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TileID.
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status registers to store credit info (buffer status)
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output ports to send ready signal to ICs
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input ports for request signals from ICs
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