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NIRGAM Class List

Here are the classes, structs, unions and interfaces with brief descriptions:
ant_hdrPacket header for ant packets
AntNet_hdrRouting header for Ant based routing algorithm
App_concatModule to define string concatenation application
App_recvModule to define sink for string concatenation application
App_sendModule to define send application for string concatenation
BaseNWTileAbstract class to represent network tile
BurstyTrafficModule to define Bursty traffic generator
CBRTrafficModule to define CBR (constant bit rate) traffic generator
Controller< num_ip >Module to represent a Controller
creditLineCredit data structure to transmit buffer status
ECCError control code
fifoFifo data structure
flitFlit data structure
flit_dataFlit header in data/tail flit
flit_hdrFlit header, depending on type of flit (hdt, head, data, tail)
flit_headFlit header in head/hdt flit
InputChannel< num_op >Module to represent an Input Channel
ipcoreModule to represent an ipcore
NoCRepresents the entire Network-on-Chip
noc_hdrPacket header for noc packets
NWTile< num_nb, num_ic, num_oc >Module to represent a tile in NoC
OE_routerClass to implement OE routing algorithm
OutputChannel< num_ip >Module to represent an Output Channel
payload_hdrPayload in head/hdt flit
pkt_hdrPacket header (depending on packet type)
routerAbstract router class
routing_hdrRouting header in flit
rt_dst_hdrRouting header for XY and OE routing algorithm
signalsSignals to connect neighboring tiles
sim_hdrHeader to record simulation data
SinkModule to define sink application for an ipcore
source_hdrRouting header for source routing algorithm
source_routerClass to implement source routing algorithm
switch_regRegister data structure
TraceTrafficModule to define trace based traffic generator
TrafficGeneratorModule to define traffic generator
VCVirtual channel (VC) data structure
VCAllocator< num_ip >Module to represent a Virtual channel allocator
XY_routerClass to implement XY routing algorithm

Generated on Mon May 7 19:03:19 2007 for NIRGAM by  doxygen