#include <InputChannel.h>
Inheritance diagram for InputChannel< num_op >:
Public Member Functions | |
SC_CTOR (InputChannel) | |
Constructor. | |
void | read_flit () |
reads flit from i/p port and calls function to store it in buffer | |
void | store_flit_VC (flit *) |
stores flit in buffer | |
void | route_flit () |
routes the flit at the front of fifo buffer | |
void | routing_src (flit *) |
routing function for algorithms containing entire path in header (source routing) | |
void | routing_dst (flit *) |
routing function for algorithms containing destination address in header | |
void | transmit_flit () |
void | setTileID (UI tileID, UI portN, UI portS, UI portE, UI portW) |
sets tile ID and id corresponding to port directions | |
void | resetCounts () |
resets buffer counts to zero | |
void | closeLogs () |
closes logfiles | |
int | reverse_route (int) |
reverses route (to be used in future) | |
Public Attributes | |
sc_in< bool > | switch_cntrl |
input clock port | |
sc_in< flit > | inport |
input data/flit port | |
sc_out< flit > | outport [num_op] |
ouput data/flit ports (one for each output channel) | |
sc_in< bool > | outReady [num_op] |
input ports for ready signal from OCs | |
sc_out< bool > | vcRequest |
output port for sending request to VCA | |
sc_in< bool > | vcReady |
input port for ready signal from VCA | |
sc_out< sc_uint< 2 > > | opRequest |
output port for sending OC requested to VCA | |
sc_in< sc_uint< VCS_BITSIZE+1 > > | nextVCID |
input port to recieve next VCID from VCA | |
sc_out< creditLine > | credit_out [NUM_VCS] |
output ports to send credit info (buffer status) to OC, VCA and Ctr | |
sc_out< request_type > | rtRequest |
output port to send request to Controller | |
sc_in< bool > | rtReady |
input port to recieve ready signal from Controller | |
sc_out< sc_uint< ADDR_SIZE > > | destRequest |
output port to send destination address to Controller | |
sc_out< sc_uint< ADDR_SIZE > > | sourceAddress |
output port to send source address to Controller | |
sc_in< sc_uint< 3 > > | nextRt |
input port to recieve routing decision (next hop) from Controller | |
VC | vc [NUM_VCS] |
Virtual channels. | |
UI | cntrlID |
Control ID to identify channel direction. | |
UI | tileID |
Tile ID. | |
UI | portN |
port number representing North output direction | |
UI | portS |
port number representing South output direction | |
UI | portE |
port number representing East output direction | |
UI | portW |
port number representing West output direction | |
UI | numBufReads |
number of buffer reads in the channel | |
UI | numBufWrites |
number of buffer writes in the channel | |
UI | numBufsOcc |
number of occupied buffers | |
UI | numVCOcc |
number of occupied virtual channels | |
ULL | sim_count |
keeps track of number of clock cycles |
This module defines an Input Channel in a network tile
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closes logfiles Method to close logfiles |
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reads flit from i/p port and calls function to store it in buffer Process sensitive to inport event Reads flit from input port and calls function to store in buffer |
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resets buffer counts to zero Method to resut buffer stats to zero |
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reverses route (to be used in future)
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routes the flit at the front of fifo buffer Process sensitive to clock Calls routing functions if head/hdt flit at the front of fifo |
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routing function for algorithms containing destination address in header Method to call controller for routing algorithms that require destination address |
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routing function for algorithms containing entire path in header (source routing) Method to call Controller for source routing |
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Constructor.
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sets tile ID and id corresponding to port directions Method to assign tile IDs and port IDs |
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stores flit in buffer Method to store flit in fifo buffer |
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transmits flit at the front of fifo to output port |
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Control ID to identify channel direction.
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output ports to send credit info (buffer status) to OC, VCA and Ctr
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output port to send destination address to Controller
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input data/flit port
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input port to recieve routing decision (next hop) from Controller
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input port to recieve next VCID from VCA
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number of buffer reads in the channel
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number of occupied buffers
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number of buffer writes in the channel
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number of occupied virtual channels
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output port for sending OC requested to VCA
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ouput data/flit ports (one for each output channel)
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input ports for ready signal from OCs
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port number representing East output direction
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port number representing North output direction
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port number representing South output direction
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port number representing West output direction
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input port to recieve ready signal from Controller
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output port to send request to Controller
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keeps track of number of clock cycles
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output port to send source address to Controller
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input clock port
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Tile ID.
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Virtual channels.
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input port for ready signal from VCA
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output port for sending request to VCA
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