NIRGAM

00001 
00002 /*
00003  * NWTile.h
00004  *
00005  * This program is free software; you can redistribute it and/or
00006  * modify it under the terms of the GNU General Public License,
00007  * version 2, as published by the Free Software Foundation.
00008  *
00009  * This program is distributed in the hope that it will be useful,
00010  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00011  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00012  * GNU General Public License for more details.
00013  *
00014  * You should have received a copy of the GNU General Public License along
00015  * with this program; if not, write to the Free Software Foundation, Inc.,
00016  * 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
00017  *
00018  * Author: Lavina Jain
00019  *
00020  */
00021 
00026 
00027 #ifndef __NW_TILE__
00028 #define __NW_TILE__
00029 
00030 #include "systemc.h"
00031 #include "../config/constants.h"
00032 #include "flit.h"
00033 #include "credit.h"
00034 #include "InputChannel.h"
00035 #include "OutputChannel.h"
00036 #include "VCAllocator.h"
00037 #include "ipcore.h"
00038 #include "Controller.h"
00039 #include "BaseNWTile.h"
00040 
00041 #define ptr (NWTile<NUM_NB, NUM_IC, NUM_OC> *)
00042 #define ptr_b (NWTile<NUM_NB_B, NUM_IC_B, NUM_OC_B> *)
00043 #define ptr_c (NWTile<NUM_NB_C, NUM_IC_C, NUM_OC_C> *)
00044 
00055 template <int num_nb = NUM_NB, int num_ic = NUM_IC, int num_oc = NUM_OC>
00056 struct NWTile : public BaseNWTile {
00057 
00058         // PORTS ////////////////////////////////////////////////////////////////////////////////////
00059         sc_in<bool>     switch_cntrl;           
00060         sc_in<flit>     ip_port[num_nb];        
00061         sc_out<flit>    op_port[num_nb];        
00062 
00063         sc_in<creditLine>       credit_in[num_nb][NUM_VCS];     
00064         sc_out<creditLine>      credit_out[num_nb][NUM_VCS];    
00065         // PORTS END ////////////////////////////////////////////////////////////////////////////////
00066 
00068         // Parameter - module name, tile id.
00069         SC_HAS_PROCESS(NWTile);
00070         NWTile(sc_module_name NWTile, UI tileID);
00071 
00072         // PROCESSES //////////////////////////////////////////////////////////////////////////////////////////
00073         void entry();           
00074         void setID(UI);         
00075         void closeLogs();       
00076         float return_latency(int port_dir);             
00077         float return_latency_flit(int port_dir);        
00078         float return_avg_tput(int port_dir);            
00079         int return_total_latency();                     
00080         int return_total_flits();                       
00081         int getportid(int port_dir);                    
00082         // PROCESS END /////////////////////////////////////////////////////////////////////////////////////
00083 
00084         // SUBMODULES /////////////////////////////////////////////////////////////////
00085         InputChannel<num_oc>    *Ichannel[num_ic];      
00086         OutputChannel<num_ic>   *Ochannel[num_oc];      
00087         VCAllocator<num_ic>     vcAlloc;                
00088         ipcore                  *ip;                    
00089         Controller<num_ic>      ctr;                    
00090         // SUBMODULES END //////////////////////////////////////////////////////////////////////////////////
00091 
00092         // SIGNALS ///////////////////////////////////////////////////////////////////////////////////
00094         sc_signal<flit> flit_sig[num_ic][num_oc];
00096         sc_signal<flit> flit_CS_IC;
00098         sc_signal<flit> flit_OC_CR;
00099 
00101         sc_signal<bool> rdy[num_ic][num_oc];
00102 
00104         sc_signal<bool> vcReq[num_ic];
00106         sc_signal<sc_uint<2> >  opReq[num_ic];
00107 
00109         sc_signal<bool> vcReady[num_ic];
00111         sc_signal<sc_uint<VCS_BITSIZE+1> >      nextvc[num_ic];
00112 
00114         sc_signal<creditLine>   creditIC_CS[NUM_VCS];
00115         //sc_signal<creditLine> creditCR_OC[NUM_VCS];
00116 
00118         sc_signal<request_type> rtReq[num_ic];
00120         sc_signal<sc_uint<ADDR_SIZE> > destReq[num_ic];
00122         sc_signal<sc_uint<ADDR_SIZE> > srcAddr[num_ic];
00123 
00125         sc_signal<bool> rtReady[num_ic];
00127         sc_signal<sc_uint<3> > nextRt[num_ic];
00128         // SIGNALS END ///////////////////////////////////////////////////////////////////////////////////////////////////
00129 
00130 };
00131 
00132 #endif